The present invention relates to a semiconductor thin film transistor, a producing method thereof, a semiconductor thin film transistor array substrate and a liquid crystal display using the semiconductor thin film transistor array substrate.
More particularly, the present invention relates to an improvement in electric characteristics of a thin film transistor, especially of a thin film transistor that is used in an active matrix type liquid crystal display, and the improvements in electric characteristics particularly being a decrease in serial resistance, a decrease in light generated current when light is irradiated, and a decrease in OFF current.
Switching elements, so-called thin film transistors (hereinafter referred to as "TFT"), that are used in active matrix type liquid crystal displays are classified, depending on the arrangement thereof, as to be either of direct stagger or inverted stagger structure. TFTs of inverted stagger structure are further classified into etching-stopper type TFT (ES-TFT) and channel etch type TFT ("CE-TFT"). FIG. 21(a) and FIG. 21(b) are sectional, explanatory view showing a conventional channel etch type TFT, and FIG. 21(a) is a sectional view showing an arrangement of an etching stopper type TFT ("ES-TFT") and FIG. 21(b) of a channel etch type TFT (CE-TFT). In FIG. 21(a)and FIG. 21(b), 201 denotes a gate electrode, 202 a gate insulating film, 207a and 207b a source electrode of two-layer structure, 207c and 207d a drain electrode of two-layer structure, 209a a channel region, 213 an etching stopper film, 214 an amorphous silicon film doped to be of n-type, 221 an insulating substrate, and 223 a channel layer, respectively.
All types of TFTs have an advantage as well as a disadvantage. For instance, since an interface between an etching stopper and an amorphous silicon layer is purely formed in an ES-TFT, characteristics of small OFF current can be obtained. However, on the other hand, it is disadvantaged in terms of small-sizing, since a patterning size of the etching stopper and separation of source electrode and drain electrode running on the etching stopper are prescribed by a transferring accuracy of a transferring device (stepper) so that small-sizing is made difficult, and further, the asymmetrical arrangement of the source electrode and the drain electrode with respect to the etching stopper may result in asymmetric characteristics. To be of asymmetric characteristics means that current-voltage current characteristics differ when the source electrodes is made to be a grounded electrode and when the drain electrode is made to be the grounded electrode. Comparing with this, a CE-TFT is advantageous when comparing with an ES-TFT since small-sizing thereof can be easily performed and the characteristics thereof are not made asymmetric; however, since separation of the source electrode and the drain electrode is performed by etching a channel region of an amorphous silicon layer in which current is supplied, an etching damage exists in the channel region whereby an increase in off current originating therein is observed. Further, the etching of the channel region necessarily results in a thick layer in order to prevent vanishing of the amorphous silicon layer in the channel region due to overetching. Such a thick layer presents such a drawback that it results in an increase in serial resistance in an area between the source electrode to the channel region and an increase in light generated current. With such a background being present, ES-TFT and CE-TFT are coexisting for structures of TFTs used in an active matrix type liquid crystal device.
It will now be explained for a conventional producing method of a CE-TFT (prior art 1) in details with reference to the drawings. FIG. 22(a) to FIG. 22(c) and FIG. 23(a) to FIG. 23(c) are a sectional, explanatory diagram showing each of the processes for producing a conventional CE-TFT. A process flow will now be explained based on FIG. 22(a) to FIG. 22(c) and FIG. 23(a) to FIG. 23(c). First, a Cr film of approximately 300 nm which is to be a gate electrode 201 is deposited onto an insulating substrate 221 made of glass or the like by sputtering method. This is shown in FIG. 22(a). Next, continuous film forming is performed by forming a silicon nitride film (SiNx) as a gate insulating film 202, an amorphous silicon layer, and an amorphous silicon layer doped to be n-type (n-type amorphous silicon layer) 214 as a channel layer 223 through plasma Chemical Vapor Deposition (CVD). The thickness of the gate insulating layer 202 is 300 to 400 nm, that of the amorphous silicon layer 200 to 400 nm, and that of the amorphous silicon layer doped to a n-type 214 (n-type amorphous silicon layer) 50 to 100 nm. This is shown in FIG. 22(b). Then, the amorphous silicon layer which is to be the channel layer and the n-type amorphous silicon layer 214 are patterned in a shape of an island through dry etching. This is shown in FIG. 22(c). Thereafter, source electrode 207a, 207b, and drain electrode 207c, 207d are formed by successively disposing Cr and Al in this order as a two-layer arrangement through sputtering, by patterning through photolithography, and by removing the Cr film and the Al film from the channel region 209 through etching. This is shown in FIG. 23(a). Next, etching through dry etching is performed to completely remove etching residues on a region between the source electrode and drain electrode, that is, on the n-type amorphous silicon layer 214 of the channel region 209. At this time, a part of the amorphous silicon layer of the channel region is also etched by overetching. The amount of overetching is 50 to 100 nm. A diagram of this process is shown in FIG. 23(b). Lastly, a passivation film 210 is formed of silicon nitride film to obtain a channel etch type TFT (CE-TFT). This is shown in FIG. 23(c).
When applying a channel etch TFT (CE-TFT) to an active matrix type liquid crystal display to improve the display characteristic thereof, the following mutually related characteristics are required to be improved by decreasing the thickness of the amorphous silicon layer that is to be the channel layer. These characteristics are (1) a decrease in serial resistance, (2) a decrease in light generated current, (3) a decrease in off current originated in junction, and (4) a decrease in off current originated in back channel interface. Each of these will now be explained in detail.
(1) Decrease in serial resistance will first be explained. As shown in the process flow of the prior art, CE-TFT requires an overetching process to completely remove residues of amorphous silicon doped to be n-type that exist between the source electrode and the drain electrode (hereinafter referred to as "between the source and the drain" ) after forming the source electrode and the drain electrode. If the residue remains without being removed, it may cause inconveniences in that the n-type amorphous silicon layer residue of low resistance may cause a short-circuit between the source and the drain or in that a silicide film formed by the amorphous silicon and Cr may cause a short-circuit between the source and the drain. Since the selective ratio of the etching for the n-type amorphous silicon layer and the amorphous silicon layer that is to be the channel region is small, the amorphous silicon layer that is to be the channel region is also etched by overetching. In order to prevent a cut between the source and the drain due to overetching, the film thickness of the amorphous silicon layer that is to be the channel region needs to be thick so that the thickness of the amorphous silicon layer which was of approximately 100 nm in an ES-TFT needs to be 200 to 400 nm in CE-TFT. Since the amorphous silicon layer that is to be the channel region is not doped and thus becomes to be a layer of high resistance, it greatly influences the TFT characteristics so that no sufficient current can be obtained in terms of current-voltage characteristics.
Next, (2) decrease in light generated current will now be explained. Since a current generated through irradiation of light (hereinafter referred to as "light generated current") causes a degradation in display characteristics, the light generated current needs to be decreased. This light generated current is closely related to the thickness of the amorphous silicon layer and increases with an increase in film thickness. As noted in item (1) decrease in serial resistance, the film thickness of the amorphous silicon layer in CE-TFT is thick so that the amount of light generated current also increases.
Next, (3) decrease in off current originated in junction will be explained. The off current needs also be decreased for improving the display characteristics. There are known several mechanisms through which off currents are generated, and one of these is a destruction of junction in an abrupt junction of n-type amorphous silicon layer and a non-doped amorphous silicon layer. In forming n-type amorphous silicon layer in conventional CE-TFTs, CVD is employed. Therefore, the interface between the n-type amorphous silicon layer and the non-doped amorphous silicon layer is made to be a so-called abrupt junction so that its impurity profile becomes steep, thereby resulting in a high electric field and thus a large OFF current. This applies also to ES-TFT. To improve such a steep of impurity profile, the impurity profile (a profile of impurity concentration) is made to be oblique by employing an ion implantation method for the doping in order to decrease a steep peak in field intensity as that in an interface of abrupt junction for ease of electric field, and by forming a so-called gentle junction, the OFF current can be decreased. In forming a junction of amorphous silicon semiconductor and a region of the amorphous silicon semiconductor doped, for instance, with n-type impurities, an "abrupt junction" is obtained by keeping the doping density constant over the whole region that is to be doped with n-type impurities and by making the doping density abruptly change at the interface of junction. On the other hand, a "gentle junction" is obtained by gradually decreasing the doping density in the region that is to be doped with n-type impurity in approaching the interface of junction, and by making the doping density gently change at the interface of the junction so that the density in the proximity of the interface of junction is made low. In terms of intensity of electric field at the interface of junction, the impurity density abruptly changes from a constant value to 0 (zero) at the interface in case of abrupt junction so that the intensity of electric field at this time shows a steep peak El with the interface between, while in case of gentle junction, a gentle and low peak E2 (E1&gt;E2) is seen since the impurity density gradually changes at the interface. As explained so far, while it is possible to decrease off current by forming a gentle junction, the restriction in that an impurity is doped also into the channel region in the process flow makes the application of ion implantation method to CE-TFT of conventional structure difficult.
Next, (4) decrease in OFF current originated in back channel interface will be explained. A back channel is a portion of the amorphous silicon layer not at the side which contacts the gate insulating film but contacting the passivation insulating film, and a back channel interface is an interface between the amorphous silicon layer and the passivation film. In CE-TFT, when separating a conductive film which has once been formed over the whole surface into source electrode and a drain electrode, etching of the amorphous silicon layer that is to be the channel region is also performed. Through this etching, unevenness is generated on the interface between the amorphous silicon layer that is to be the channel region and the passivation film, and defaults due to damages caused by plasma at etching or interface levels due to dangling bonds of atoms are formed so that an increase in OFF current is seen with this interface level being a pass.
The present invention has been made with the aim of providing a thin film transistor of an arrangement which enables forming of a thin amorphous silicon layer, gentle impurity profile and a pure back channel interface, and a producing method thereof to solve the problems of the prior art 1.
Further, a matrix type liquid crystal display is usually arranged in that a display material such as liquid crystal is interposed and held between two substrates, that is, a thin film transistor array substrate (semiconductor TFT array substrate, or TFT array substrate) provided with, for instance, a thin film transistor of semiconductor thin film (semiconductor TFT) and an opposing substrate, wherein voltage is selectively impressed to each pixel of the display material. The opposing substrate is provided with an opposing electrode, color filter, black matrix or the like. Such a liquid crystal display (LCD) employing such a TFT array substrate will be hereinafter referred to as "TFT-LCD".
As shown in an equalizing circuit of FIG. 24, pixels are arranged in a matrix manner in the TFT array substrate. FIG. 24 is a circuit diagram showing an example of an electric equivalent circuit for a TFT formed on a conventional TFT array substrate.
In FIG. 24, numeral 10 denotes a TFT, numeral 11 a storage capacitance (hereinafter referred to as "Cs capacitance"), G1, G2, and G3 a scanning signal line, S1, S2, and S3 an image signal line, and Cs1, Cs2, and Cs3 a Cs wiring for forming storage capacitance. A pixel electrode is formed of a transparent electrode such as ITO (indium tin oxide), and controls charge/discharge of charge to the pixel electrode with the TFT serving as a switching element. ON/OFF control of the TFT is performed by using the scanning signal line as a gate electrode. The pixel electrode is connected to the image signal line through the TFT and according to the height of signal levels of the image signal, the amount of charge supplied to the pixel electrode varies whereby the potential of the pixel electrode is set. Depending on the voltage between the pixel electrode and opposing electrode, the displacement amount of the liquid crystal varies whereby the amount of light transmission from the rear face varies. Therefore, by controlling the signal level of the image signal line, changes in optical signal are controlled and displayed as images.
In order to improve the quality of image, it is required to keep fluctuations in the potential of the pixel electrode (hereinafter referred to as "pixel potential") caused by changes in signal level of, for instance, the scanning signal line as small as possible. Therefore, a Cs capacitance 11 is provided for the pixel electrode to provide a large total capacitance related to the pixel electrode. The Cs capacitance is formed by providing an insulating film between a Cs line which is equal in potential as the opposing electrode and the pixel electrode.
Next, a pixel layout in a conventional TFT array substrate is shown in FIG. 25, and an example of a TFT manufactured based on the pixel layout is shown in FIG. 26(a), FIG. 26(b), FIG. 27(a) and FIG. 27(b) which show sectional arrangements thereof. Further, an example of a conventional manufacturing method of a TFT is shown in FIG. 28(a) to FIG. 28(f) and FIG. 29(a) to FIG. 29(d).
FIG. 25 is a plan, explanatory view of a conventional pixel layout, and in FIG. 25, 6 denotes a pixel electrode, 7 a drain electrode, 8 a source electrode, 13 a gate line, 14 a source line, 15 a Cs wiring and 16 a semiconductor thin film. FIG. 26(a), FIG. 26(b), FIG. 27(a) and FIG. 27(b) are sectional, explanatory diagram showing a sectional arrangement of a TFT as shown in FIG. 25 cut along line A--A. In FIG. 26(a), FIG. 26(b), FIG. 27(a) and FIG. 27(b), numeral 1 denotes a glass substrate, numeral 2 denotes a gate electrode of the TFT, numeral 3 denotes a gate insulating film, numeral 4 denotes an i-layer, numeral 5 denotes an n-layer, numeral 6 denotes a pixel electrode, numeral 7 denotes a drain electrode, numeral 8 denotes a source electrode, numeral 9 denotes a DC cut film employed as the insulating film, reference character Rss denotes an ON resistance at the side of the source electrode, reference character Rsd denotes an ON resistance at the side of the drain electrode, and reference character Rsc denotes an ON resistance at the side of the channel. Reference character D denotes connection to the drain electrode, reference character G denotes connection to the gate electrode, and reference character S denotes connection to the source electrodes. Further, the i-layer is a layer of intrinsic semiconductor, and the n-layer is a layer of n-type semiconductor. The DC cut film 9 is provided for protecting the metal wiring in underlying layers and formed of silicon nitride film (SiNx) by, for instance, a plasma CVD method. The DC cut film may also be a passivation film. It should be noted that, in this specification, a region on which the source electrode is formed is called a source region, a region on which the drain electrode is formed a drain region, and a region between the source electrode and drain electrode a channel region. Also, a channel formed in a region on the i-layer opposite to the gate insulating film is called back channel. Further, a region in which the pixel electrode is formed is called a pixel region.
FIG. 28(a) to FIG. 28(f) and FIG. 29(a) to FIG. 29(d) are a sectional, explanatory diagram showing each of the processes performed in a conventional manufacturing method of a TFT. Portions of FIG. 28(a) to FIG. 28(f) and FIG. 29(a) to FIG. 29(d) that are identical to those as shown in FIG. 25, FIG. 26(a), FIG. 26(b), FIG. 27(a) and FIG. 27(b) are indicated by the same reference numerals and 111, 112, 113, and 114 denote resists. In FIG. 28(a), a first metal thin film is formed onto glass substrate 1 that is to be an gate electrode, and after developing a pattern of resist 111, the first metal thin film is etched to form an gate electrode 2 as shown in FIG. 28(b). After removing resist 111, a gate insulating film 3, i-layer 4 and n-layer 5 are formed in this order from the bottom as shown in FIG. 28(c), and after developing a pattern of resist 112, the i-layer 4 and n-layer 5 are etched as shown in FIG. 28(d). After removing resist 112, an ITO thin film is formed that is to be a pixel electrode as shown in FIG. 28(e), and by etching the ITO thin film after developing a resist 113, a pixel electrode 6 is formed as shown in FIG. 28(f). After removing the resist 113, a metal thin film is formed that is to be the source electrode and the drain electrode as shown in FIG. 29(a) and by etching after developing a pattern of resist 114, the source electrode and drain electrode are formed as shown in FIG. 29(b). Further, by etching the entire n-layer and a part of the i-layer and the side of the back channel of the TFT (back channel etching) and removing, as shown in FIG. 29(c), the resist, a DC cut film 9 is formed as an insulating film as shown in FIG. 29(d).
The TFT, gate line, source line, and other common line are thus formed in a form of an array on the glass substrate to provide a display region, and an input terminal, an auxiliary line and an insulating film are arranged in the periphery of the display region. At this time, conductive layers or insulating layers may be provided, when required, to make each of the functions work. The opposing substrate is provided thereon with an opposing electrode, a color filter and a black matrix.
After manufacturing a TFT array substrate and an opposing substrate, both substrates are stuck together at their circumference with a desired space formed therebetween so that a liquid crystal material may be implanted between the two substrates, a liquid crystal material is then implanted between the two substrates to obtain a liquid crystal display.
The arrangement and function of a conventional TFT will now be explained taking a case of prior art 2 as an example. When charging the pixel electrode 6 with electric charge in FIG. 26(a), the TFT is turned to an ON condition by impressing a voltage of approximately 9 V to the source electrode 8 and a positive voltage of approximately 20 V to the gate electrode 2. On the other hand, the drain electrode 7 and the pixel electrode 6 are charged to nearly 9 V. Thereafter, when the potential of the pixel electrode has been sufficiently raised, a negative voltage of approximately -5 V is impressed to the gate electrode 2 to turn the TFT off to confine electric charge in the pixel.
When performing the series of actions until confinement of electric charge in the pixel has been achieved, the degree of raising of the pixel electrode potential depends largely on the size of volume connected to the pixel electrode 6 and the ON resistance of the TFT. The ON resistance of TFT in a conventional TFT may be virtually considered to be cut off a section in the proximity of the channel of the TFT as in FIG. 26(b) and as to be separated into each component of the resistance in accordance with the sectional arrangement, as shown in FIG. 27(a). That is, the ON resistance is the Rss at the side of the source electrode, Rsc of the channel portion and Rsd at the side of the drain electrode. Since the drain electrode 7 and source electrode 8 are made of metal thin film, the resistance of the n-layer 5 provided in an underlying layer of these electrodes is sufficiently small than compared to Rss, Rsc and Rsd, the resistance of the n-layer 5 is of ignorable level as an ON resistance of TFT.
Therefore, the TFT may be expressed to be an equivalent circuit in which the side of the drain electrode is connected to Rsd resistance, and the side of the source electrode to a Rss resistance, as shown in FIG. 27(b). The symbolic expressions in circles representing terminals of the circuit as shown in FIG. 27(b) denote connection to the drain electrode, connection to the source electrode, and connection to the gate electrodes, respectively. A conventional TFT presented a drawback in that a large resistance Rss and Rsd resulted in a large ON resistance, whereby the pixel electrode could not be sufficiently charged within a specified time.
A conventional TFT also presented a drawback that the ON resistance was high and the driving performance of the TFT poor, because the Rss and Rsd had resistance values of the same level as the Rsc. This was because the underlying layer of the source electrode and the underlying layer of the drain electrode were provided with n-layer and i-layer in this order from the side of the source electrode and drain electrode and the channel region was comprised of i-layer, there existed an ON resistance Rss in the underlying layer of the source electrode, an ON resistance Rsd in the underlying layer of the drain electrode and a resistance Rsc in the channel region.
In the TFT arrangement of a conventional TFT array substrate, a large serial resistance is connected to the side of the source electrode and the side of the drain electrode of the TFT whereby the ON resistance of the TFT is high. Therefore, a long time was necessary to charge the pixels with a specified potential. With an increase in number of display pixels of the TFT-LCD from XGA (extended graphics array), SXGA (super extended graphics array), and to UXGA (ultra extended graphics array), the time for charging assigned per pixel will become short, whereby sufficient charge within a specified time was difficult to be achieved and thus caused a degradation in display quality.
Characteristics of the TFT largely depend on the thickness of the gate insulating film, the thickness of the i-layer underlying the source electrode or the drain electrode that constitute the TFT, or the thickness of the i-layer of the channel portion after etching (hereinafter, the film thickness after etching will be referred to as "remaining film thickness"). As the size of TFT ally substrates increases, the range of TFT characteristics within the substrate surface is largely varied depending on whether the range of variations in operating conditions can be made uniformly, that is, whether a film can be uniformly formed in the substrate surface or whether etching can be uniformly performed in the substrate surface. However, since the entire n-layer at the side of the back channel of the whole TFT of the substrate surface needs to be removed in back channel etching, it is usually required to set a rather large etching time than a time required for removing the entire n-layer in view of the range of variation in the film thickness of the n-layer as well as the range of variation in the etching action. Therefore, the i-layer in the channel region of the TFT is also thickly etched, and a variation is caused also in the remaining film thickness. Accordingly, it resulted in a variation of TFT characteristics in the substrate surface and also in a range in uniformity of the display characteristics of the TFT-LCD.
The present invention has been made to solve the problems of the prior art 2 in that a range in uniformity of the above-described display characteristics is caused, and it is an object of the present invention to provide a TFT capable of decreasing ON resistance of TFT, and of making a range of TFT characteristics small, a producing method thereof, and a TFT array substrate and by improving the driving performance and the uniformity of TFT characteristics in the display surface to realize a TFT-LCD of high display quality.